The CLB, or Configurable Logic Block, constitutes the basic FPGA cell. It consists of two 16-bit function generators (F or G), one 8-bit function generator (H), two registers (flip-flops or latches), and reprogrammable routing controls (multiplexors).

onfigurable ogic lock. The CLB constitutes the basic FPGA cell. The FPGA is an array of CLBs organized in columns and rows on the silicon die. CLBs are used to implement macros and other designed functions. They provide the physical support for an implemented and downloaded design. They have inputs on each side, and this versatility makes them flexible for the mapping and partitioning of logic.

Configurable Logic Block. Xilinx-specific name for a block of logic surrounded by routing resources. A CLB contains 2 or 4 look-up-tables function generators) plus 2 or 4 flip-flops.

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A 'hundred' pounds, which could mean 100, 112, 120 or even 124.