A dedicated channel between the CPU and a Level 2 cache. The so-called dual independent bus (DIB) architecture allows a processor to use both this and the frontside bus (which connects the CPU with main memory) simultaneously. See also Frontside Bus.
There are two types of buses that carry data to and from a computer's CPU. T...
A special bus designed to attach the microprocessor directly to the cache memory in a Dual Independent Bus (DIB) architecture system. The frontside bus connects the microprocessor to the main system memory. Used in Intel Pentium II and later systems for increased performance. Prior to the DIB architecture, the system bus was used for both purposes.
Between the CPU and L2 cache. Same speed as the CPU on a Pentium Pro, half speed on a PII and none on a Celeron. This wittily named component had Intel's motherboard designers falling out of their high chairs. This is because their average age is 8.
In a personal computer with an Intel processor chipset that includes a Dual Independent Bus (DIB), the frontside bus is the data path and physical interface between the processor and the main memory (RAM). The backside bus is the data path and physical interface between the processor and the L1 and L2 memory. Both the frontside bus and the backside bus can be in use at the same time, meaning that the processor gets more done in a given number of pulses per second (see clock speed).
In some architectures, such as Socket 7, the speed of the backside bus determined how fast the microprocessor could talk to its external L2 cache. Newer...
The data path between the microprocessor and the L1 and L2 cache. Runs at the PC's core clock speed. It is the fastest bus in your PC.
(BSB) - The data path that runs between the CPU and L2 cache.
An interface that connects the L1 and L2 memory.
In computer microprocessor architecture, a backside bus is a bus dedicated to the purpose of connecting the processor to an off-chip bank of cache memory. This is an improvement over the older practice of accessing the cache over the frontside bus (FSB) because it reduces the usage of the FSB, which is typically a severe bottleneck in most modern systems.