A deductive, top-down method of analyzing system design and performance. It involves specifying a top event to analyze, followed by identifying all of the associated elements in the system that could cause that top event to occur. Fault tree analyses are generally performed graphically using a logical structure of AND and OR gates. Sometimes certain elements, or basic events, may need to occur together in order for that top event to occur. In this case, these events would be arranged under an AND gate, meaning that all of the basic events would need to occur to trigger the top event. If the basic events alone would trigger the top event, then they would be grouped under an OR gate. The entire system as well as human interactions would be analyzed when performing a fault tree analysis.